The present invention relates to a semiconductor memory and, more particularly, to an improved semiconductor memory achieving high integration, such as a static RAM formed using MOS transistors.
In a static RAM, one memory cell is defined by a bistable flip-flop and is generally constituted by six elements. FIG. 1 is an equivalent circuit diagram of a memory cell used in a known E/R type static RAM. As illustrated, the memory cell is composed of a total of six elements, that is, two driver elements defined by enhancement type MOS transistors Q.sub.1 and Q.sub.2 that constitute a flip-flop, two load elements defined by resistors R.sub.1, and R.sub.2 and two transfer gate elements for address selection which are defined by enhancement type MOS transistors Q.sub.3 and Q.sub.4. In the figure, the reference character W denotes a word line, D, D data lines, GND a ground potential, Vcc a power supply potential, and N.sub.1, N.sub.2 nodes. These elements are formed so as to be appropriately arranged on a semiconductor substrate. Generally, in a MOS semiconductor memory, the source and drain regions of the enhancement type MOS transistors Q.sub.1 to Q.sub.4 are formed within the semiconductor substrate, and the gate electrodes thereof are formed using a first-level polycrystalline silicon layer. The resistors R.sub.1 and R.sub.2 are formed within a second-level polycrystalline silicon layer. Such a configurational structure enables the static RAM to have a relatively high integration density.
However, the great demand for an even higher integration of semiconductor integrated circuit devices requires further miniaturization and an improvement in the configurational structure of elements within each memory cell. Under these circumstances, a method wherein one of the driver MOS transistors is formed in silicon on an insulator (Silicon On Insulator; SOI) has been proposed (see Japanese Patent Laid-Open No. 111458/1985). More specifically, a part of the first-level polycrystalline silicon stacked on a field insulator film is formed into a single crystal by means of the laser annealing method, and the source and drain regions of one of the driver MOS transistors are formed in this single crystal region. The gate electrode of this driver MOS transistor is formed using a second-level polycrystalline silicon layer. In this way, the element area is reduced, and the number of contacts between the gates and drains of the driver MOS transistors is decreased, thereby improving the reliability.
In the above-described structure wherein one of the driver MOS transistors is formed in SOI, the driver MOS transistor formed in SOI is disposed in a region which has conventionally been occupied by a driver MOS transistor formed within the semiconductor substrate. Therefore, it is essentially impossible to expect a substantial reduction in the element area. Further, since the described element structure causes a reduction in the junction capacitance of the node to which is connected the drain of the driver MOS transistor formed in SOI, the required amount of signal charge at this node cannot be ensured, so that there is a fear of data being readily lost as a result of disturbance such as by alpha particles. In addition, since the two driver MOS transistors have different substrates, it is difficult to make the characteristics of these transistors uniform, so that it is difficult to form a memory cell which is capable of performing a balanced operation.